1. Field of the Invention
This invention relates generally to electronic information storages devices containing bistable cells and in particular to semiconductor circuits for simultaneously erasing all the information stored in the bistable cells of such devices and entering a predetermined new pattern of information into the cells.
2. Prior Art
In some prior art cellular information storage devices, each cell in the device has to be addressed sequentially to erase the information stored in the device so that a new operation can be initiated with either a clean slate or a predetermined pattern of information. This technique is unduly time consuming.
More recently, electronic circuits have come into use in which all the information stored in the cells of an information storage device is simultaneously erased and then simultaneously replaced with a predetermined new pattern of information. The term "set" refers to the entering or writing of "1's" or high logic states into the storage device. The term "reset" refers to the writing of "0's" or low logic states into the storage device. In certain of the more recent circuits, either "set" or "reset" states, or a combination thereof, may be introduced simultaneously into a storage device. That is, the new pattern of information entered into the storage device may consist of all "0's" or all "1's" or a predetermined combination of "1's" and "0's."
An example of the more recent circuits is disclosed by G. W. Brown in U.S. Pat. No. 4,035,784, "Asymmetrical Memory Cell Arrangement," assigned to the assignee of the present invention. Brown employs an arrangement of asymmetrical memory cells in which the leading edge of a pulse causes all the memory cells to be deselected--i.e., not addressed--by diverting all the bit-line and cell-sustaining word-line currents away from each memory cell. During the trailing edge of the pulse, the word-line current then flows through a predetermined side of each cell to establish a desired logic state in the cell. The predetermined side of the cell is determined by the asymmetrical nature of the transistor emitters in each of the Brown cells.
To create the desired logic state in each cell in the Brown circuit, the word-line current resulting from the trailing edge of the pulse must be established before the bit-line current is reestablished in each cell. This makes the Brown device sensitive to race conditions. It is also sensitive to device-leakage currents.
As another example, R. S. Dunn et al. in U.S. Pat. No. 3,634,833, "Associative Memory Circuit," disclose the use of multiple-emitter transistors in a memory circuit.